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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 0 1 publication order number: pca9517a/d pca9517a level-translating i 2 c-bus repeater the pca9517a is an i 2 c ? bus repeater that provides level shifting between low voltage (down to 0.9 v) and higher voltage (2.7 v to 5.5 v) for i 2 c ? bus or smbus applications. features ? 2 channel, bidirectional buffer isolates capacitance and allows 400 pf on either side of the device ? voltage level translation from 0.9 v to 5.5 v and from 2.7 v to 5.5 v ? footprint and functional replacement for pca9515/15a ? i 2 c ? bus and smbus compatible ? active high repeater enable ? open ? drain inputs/outputs ? lock ? up free operation ? supports arbitration and clock stretching across the repeater, and multiple masters ? i 2 c and smbus scl clock frequency up to 1 mhz (the maximum system operating frequency may be less than 1 mhz because of the delays added by the repeater.) ? powered ? off high ? impedance i 2 c ? bus pins ? a side operating supply voltage range of 0.9 v to 5.5 v ? b side operating supply voltage range of 2.7 v to 5.5 v ? 5 v tolerant i 2 c ? bus and enable pins ? available in: micro ? 8, soic8 ? esd performance: 8 kv hbm, 700 v mm, 2000 v cdm ? these are pb ? free devices micro8 dm suffix case 846a http://onsemi.com a = assembly location l = wafer lot m = date code y = year w = work week = pb ? free package marking diagrams see detailed ordering and shipping information on page 12 of this data sheet. ordering information 9517 ayw 1 8 (note: microdot may be in either location) 1 8 soic ? 8 case 751 9517 ayww 1 8
pca9517a http://onsemi.com 2 general description the pca9517a is an i 2 c ? bus repeater that provides level shifting between low voltage (down to 0.9 v) and higher voltage (2.7 v to 5.5 v) for i 2 c ? bus or smbus applications. while retaining all the operating modes and features of the i 2 c ? bus system during the level shifts, it also permits extension of the i 2 c ? bus by providing bidirectional buffering for both the data (sda) and the clock (scl) lines, thus enabling two buses of 400 pf. using the pca9517a enables the system designer to isolate two halves of a bus for both voltage and capacitance. the sda and scl pins are overvoltage tolerant and are high ? impedance when the pca9517a is unpowered. the 2.7 v to 5.5 v bus b side drivers behave much like the drivers on the pca9515a device, while the adjustable voltage bus a side drivers drive more current and eliminate the static offset voltage. this results in a low on the b side translating into a nearly 0 v low on the a side which accommodates smaller voltage swings of lower voltage logic. the static offset design of the b side pca9517a i/o drivers prevents them from being connected to another device that has a rise time accelerator including the pca9510, pca9511, pca9512, pca9513, pca9514, pca9515a, pca9516a, pca9517a (port b), or pca9518. the a side of two or more pca9517as can be connected together, however, to allow a star topology with the a side on the common bus, and the a side can be connected directly to any other buffer with static or dynamic offset voltage. multiple pca9517as can be connected in series, a side to b side, with no build ? up in offset voltage with only time ? of ? flight delays to consider. the pca9517a drivers are not enabled unless the bus is idle, v cc(a) is above 0.8 v and v cc(b) is above 2.5 v. the en pin can also be used to turn the drivers on and off under system control. caution should be observed to only change the state of the enable pin when the bus is idle. the output pull ? down on the b side internal buffer low is set for approximately 0.5 v, while the input threshold of the internal buffer is set about 70 mv lower (0.43 v). when the b side i/o is driven low internally, the low is not recognized as a low by the input. this prevents a lock ? up condition from occurring. the output pull ? down on the a side drives a hard low and the input level is set at 0.3 v cc(a) to accommodate the need for a lower low level in systems where the low voltage side supply voltage is as low as 0.9 v. block diagram figure 1. block diagram of pca9517a
pca9517a http://onsemi.com 3 pin assignment figure 2. soic8 / micro8 pca9517a pin descriptions symbol pin description v cc(a) 1 a ? side supply voltage (0.9 v to 5.5 v) scla 2 open ? drain i/o, serial clock a ? side bus sdaa 3 open ? drain i/o, serial data a ? side bus gnd 4 ground en 5 active ? high repeater enable sdab 6 open ? drain i/o, serial data b ? side bus sclb 7 open ? drain i/o, serial clock b ? side bus v cc(b) 8 b ? side supply voltage (2.7 v to 5.5 v) functional description please refer to figure 1 ?block diagram of pca9517a?. the pca9517a enables i 2 c ? bus or smbus translation down to v cc(a) as low as 0.9 v without degradation of system performance. the pca9517a contains two bidirectional open ? drain buffers specifically designed to support up ? translation/down ? translation between the low voltage (as low as 0.9 v) and a 3.3 v or 5 v i 2 c ? bus or smbus. all inputs and i/os are overvoltage tolerant to 5.5 v even when the device is unpowered (v cc(b) and/or v cc(a) = 0 v). the pca9517a includes a power ? up circuit that keeps the output drivers turned off until v cc(b) is above 2.5 v and the v cc(a) is above 0.8 v. v cc(b) and v cc(a) can be applied in any sequence at power ? up. after power ? up and with the enable (en) high, a low level on port a (below 0.3 v cc(a) ) turns the corresponding port b driver (either sda or scl) on and drives port b down to about 0.5 v. when port a rises above 0.3 v cc(a) , the port b pull ? down driver is turned off and the external pull ? up resistor pulls the pin high. when port b falls first and goes below 0.3v cc(b) , the port a driver is turned on and port a pulls down to 0 v. the port b pull ? down is not enabled unless the port b voltage goes below 0.4 v. if the port b low voltage does not go below 0.5 v, the port a driver will turn off when port b voltage is above 0.7 v cc(b) . if the port b low voltage goes below 0.4 v, the port b pull ? down driver is enabled and port b will only be able to rise to 0.5 v until port a rises above 0.3 v cc(a) , then port b will continue to rise being pulled up by the external pull ? up resistor. the v cc(a) is only used to provide the 0.3 v cc(a) reference to the port a input comparators and for the power good detect circuit. the pca9517a logic and all i/os are powered by the v cc(b) pin. enable pin (en) the en pin is active high with an internal pull ? up to v cc(b) and allows the user to select when the repeater is active. this can be used to isolate a badly behaved slave on power ? up until after the system power ? up reset. it should never change state during an i 2 c ? bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the i 2 c ? bus parts being enabled. the en pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures. i 2 c ? bus systems as with the standard i 2 c ? bus system, pull ? up resistors are required to provide the logic high levels on the buffered bus (standard open ? collector configuration of the i 2 c ? bus). the size of these pull ? up resistors depends on the system, but each side of the repeater must have a pull ? up resistor.
pca9517a http://onsemi.com 4 this part designed to work with standard ? mode, fast ? mode and fast ? mode+ i 2 c ? bus devices, in addition to smbus devices. standard ? mode i 2 c ? bus devices only specify 3 ma output drive; this limits the termination current to 3 ma in a generic i 2 c ? bus system where standard ? mode devices and multiple masters are possible. under certain conditions, higher termination currents can be used. application design ? in information a typical application is shown in figure 3. in this example, the system master is running on a 3.3 v i2c ? bus while the slave is connected to a 1.2 vbus. both buses run at 400 khz. master devices can be placed on either bus. figure 3. typical application the pca9517a is 5 v tolerant, so it does not require any additional circuitry to translate between 0.9 v to 5.5 v bus voltages and 2.7 v to 5.5 v bus voltages. when the a side of the pca9517a is pulled low by a driver on the i 2 c ? bus, a comparator detects the falling edge when it goes below 0.3 v cc(a) and causes the internal driver on the b side to turn on, causing the b side to pull down to about 0.5 v. when the b side of the pca9517a falls, first a cmos hysteresis type input detects the falling edge and causes the internal driver on the a side to turn on and pull the a side pin down to ground. in order to illustrate what would be seen in a typical application, refer to figures 4 and 5. if the bus master in figure 3 were to write to the slave through the pca9517a, waveforms shown in figure 4 would be observed on the a bus. this looks like a normal i 2 c ? bus transmission except that the high level may be as low as 0.9 v, and the turn on and turn off of the acknowledge signals are slightly delayed. figure 4. bus a (0.9 v to 5.5 v bus) waveform on the b bus side of the pca9517a (figure 5), the clock and data lines would have a positive offset from ground equal to the v ol of the pca9517a. after the 8th clock pulse, the data line will be pulled to the v ol of the slave device, which is very close to ground in this example. at the end of the acknowledge, the level rises only to the low level set by the driver in the pca9517a for a short delay while the a bus side rises above 0.3v cc(a) , then it continues high. it is important to note that any arbitration or clock stretching events require that the low level on the b bus side at the input of the pca9517a (v il ) be at or below 0.4 v to be recognized by the pca9517a and then transmitted to the a bus side.
pca9517a http://onsemi.com 5 figure 5. bus b (2.7 v to 5.5 v bus) waveform multiple pca9517a a sides can be connected in a star configuration (figure 6), allowing all nodes to communicate with each other. figure 6. typical star application multiple pca9517as can be connected in series (figure 7) as long as the a side is connected to the b side. i 2 c ? bus slave devices can be connected to any of the bus segments. the number of devices that can be connected in series is limited by repeater delay/time ? of ? flight considerations on the maximum bus speed requirements.
pca9517a http://onsemi.com 6 figure 7. typical series application figure 8. typical application of pca9517a driving a short cable
pca9517a http://onsemi.com 7 maximum ratings symbol parameter value unit v cc(b) supply voltage port b ? 0.5 to +7.0 v v cc(a) supply voltage port a ? 0.5 to +7.0 v v i/o input/output pin voltage sdab, sclb, en ? 0.5 to +7.0 v i i/o input/output current sdaa, sdab, scla, sclb 50 ma i i input current en 50 ma i cc dc supply current 100 ma i gnd dc ground current 100 ma t stg storage temperature range ? 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance soic8 (note 1) miicro8 146 205 c/w p d power dissipation in still air at 85 c soic8 miicro8 856 609 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body mode (note 2) machine model (note 3) charged device model (note 4) > 8000 > 700 >2000 v i latchup latchup performance above v cc and below gnd at 125 c (note 5) 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm ? by ? 1 inch, 2 ounce copper trace no air flow. 2. tested to eia / jesd22 ? a114 ? a. 3. tested to eia / jesd22 ? a115 ? a. 4. tested to jesd22 ? c101 ? a. 5. tested to eia / jesd78. recommended operating conditions symbol parameter min max unit v cc(b) supply voltage port b 2.7 5.5 v v cc(a) (note 6) supply voltage port a 0.9 5.5 v v i/o input/output pin voltage 0 5.5 v t a operating free ? air temperature ? 40 +85 c 6. low level supply voltage.
pca9517a http://onsemi.com 8 dc characteristics v cc(b) , v cc(a) = 2.7 v to 5.5 v, unless otherwise specified. symbol parameter conditions t a = ? 40 c to +85 c unit min typ max supplies i cc(a) supply current port a pin v cc(a) 1 ma i cch high ? level supply current both channels high; v cc = 5.5 v; sdan = scln = v cc 1.5 5 ma i ccl low ? level supply current both channels low; v cc = 5.5 v; one sda and scl = gnd; other sda and scl open 1.5 5 ma i cc(a)c contention port a supply current v cc = 5.5 v; sdan = scln = v cc 1.5 5 ma input / output sdab, sclb v ih high ? level input voltage 0.7 x v cc(b) v v il (note 7) low ? level input voltage 0.3 x v cc(b) v v ilc contention low ? level input voltage ? 0.5 0.4 v v ik input clamping voltage i i = ? 18 ma ? 1.2 v v ol low ? level output voltage i ol = 100 a or 6 ma 0.43 0.52 0.6 v v ol ? v ilc (note 8) difference between low ? level output voltage and low ? level input voltage contention 80 mv i li input leakage current v i = 3.6 v 1 a i il low ? level input current sda, scl, v i = 0.2 v 10 a i loh high ? level output leakage current v o = 3.6 v 10 a c i/o input/output capacitance v i = 3 v or 0 v; v cc = 3.3 v 5 7 pf v i = 3 v or 0 v; v cc = 0 v 5 7 input / output sdaa, scla v ih high ? level input voltage 0.7 x v cc(a) v v il (note 9) low ? level input voltage 0.3 x v cc(a) v v ik input clamping voltage i i = ? 18 ma ? 1.2 v v ol low ? level output voltage i ol = 6 ma 0.1 0.2 v i li input leakage current v i = 3.6 v 1 a i il low ? level input current sda, scl, v i = 0.2 v 10 a i loh high ? level output leakage current v o = 3.6 v 10 a c i/o input/output capacitance v i = 3 v or 0 v; v cc = 3.3 v 5 7 pf v i = 3 v or 0 v; v cc = 0 v 5 7 input en v ih high ? level input voltage 0.7 x v cc(b) v 7. v il specification is for the first low level seen by the sdab/sclb lines. v ilc is for the second and subsequent low levels seen by the sdab/sclb lines. 8. guaranteed by design, not production tested. 9. v il for port a with envelope noise must be below 0.3 v cc(a) for stable performance.
pca9517a http://onsemi.com 9 dc characteristics v cc(b) , v cc(a) = 2.7 v to 5.5 v, unless otherwise specified. symbol unit t a = ? 40 c to +85 c conditions parameter symbol unit max typ min conditions parameter input en v il low ? level input voltage 0.3 x v cc(b) v i li input leakage current v i = v cc 1 a i il low ? level input current v i = 0.2 v, en; v cc = 3.6 v ? 10 ? 35 a c i input capacitance v i = 3 v or 0 v 6 7 pf 7. v il specification is for the first low level seen by the sdab/sclb lines. v ilc is for the second and subsequent low levels seen by the sdab/sclb lines. 8. guaranteed by design, not production tested. 9. v il for port a with envelope noise must be below 0.3 v cc(a) for stable performance.
pca9517a http://onsemi.com 10 ac characteristics v cc = 2.7 v to 5.5 v, unless otherwise specified. (notes 10 and 11) symbol parameter conditions t a = ? 40 c to +85 c unit min typ (note 12) max t plh (note 13) low ? to ? high propagation delay b ? side to a ? side; figure 11 100 170 250 ns t phl (note 14) high ? to ? low propagation delay b ? side to a ? side; figure 9 ns v cc(a) 2.7 v 10 80 110 v cc(a) 3.0 v 5 66 300 t tlh (note 14) low ? to ? high output transition time a ? side; figure 9 10 20 30 ns v cc(a) < 2.7 v 5 20 30 v cc(a) > 3.0 v 10 50 70 t thl (note 14) high ? to ? low output transition time a ? side; figure 9 ns v cc(a) 2.7 v 77 105 v cc(a) > 3.0 v 70 105 t plh (note 15) low ? to ? high propagation delay a ? side to b ? side; figure 10 25 53 150 ns t phl (note 15) high ? to ? low propagation delay a ? side to b ? side; figure 10 60 79 230 ns t tlh low ? to ? high output transition time b ? side; figure 10 120 140 170 ns t thl high ? to ? low output transition time b ? side; figure 10 1 48 90 ns t su (note 16) setup time en high before start condition 100 ns t h (note 16) hold time en high after stop condition 160 ns 10. times are specified with loads indicated in figure 12. different load resistance and capacitance will alter the rc time cons tant, thereby changing the propagation delay and transition times. 11. pull ? up voltages are v cc(a) on the a side and v cc(b) on the b side. 12. typical values were measured with v cc(a) = 3.3 v at t amb = 25 c, unless otherwise noted. 13. the t plh delay data from b side to a side is measured at 0.5 v on the b side to 0.5 v cc(a) on the a side when v cc(a) is less than 2 v, and 1.5 v on the a side if v cc(a) is greater than 2 v. 14. typical value measured with v cc(a) = 2.7 v at t amb = 25 c. 15. the propagation delay data from a side to b side is measured at 0.3 v cc(a) on the a side to 1.5 v on the b side. 16. the enable pin, en, should only change state when the global bus and the repeater port are in an idle state. ac waveforms figure 9. propagation delay and transition times; b ? side to a ? side figure 10. propagation delay and transition times; a ? side to b ? side
pca9517a http://onsemi.com 11 figure 11. propagation delay; b ? side to a ? side test setup pulse generator r t v cc(a) r l pulse generator r t v cc(b) r l v cc(a) v cc(a) v cc(b) c l c l figure 12. test circuit for open ? drain outputs
pca9517a http://onsemi.com 12 ordering information device package shipping pca9517adr2g in development soic8 (pb ? free) 3000 / tape & reel PCA9517ADMR2G micro ? 8 (pb ? free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
pca9517a http://onsemi.com 13 package dimensions micro8 case 846a ? 02 issue j s b m 0.08 (0.003) a s t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. b e pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane a a1 c l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max min millimeters ?? ?? 1.10 ?? inches a1 0.05 0.08 0.15 0.002 b 0.25 0.33 0.40 0.010 c 0.13 0.18 0.23 0.005 d 2.90 3.00 3.10 0.114 e 2.90 3.00 3.10 0.114 e 0.65 bsc l 0.40 0.55 0.70 0.016 ?? 0.043 0.003 0.006 0.013 0.016 0.007 0.009 0.118 0.122 0.118 0.122 0.026 bsc 0.021 0.028 nom max 4.75 4.90 5.05 0.187 0.193 0.199 h e h e d d e 8x 0.48 0.65 pitch 5.25 8x 0.80 dimension: millimeters recommended
pca9517a http://onsemi.com 14 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 pca9517a/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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